UPF & SPECIAL CELLS FOR POWER PLANNING

 Unified Power Format (UPF):

UPF is an IEEE standard and developed by members of Accellera.UPF is designed to reflect the power intent of a design at a relatively high level.

UPF scripts describe which power rails should be routed to individual blocks, when blocks are expected to be powered up or shut down, how voltage levels should be shifted as signals cross from one power domain to another and whether measures should be taken to retain register and memory-cell contents if the primary power supply to a domain is removed.

The backbone of UPF (Synopsys), as well as the similar Common Power Format (CPF) (cadence), is the Tool Control Language (TCL). The TCL command “create_power_domain”, used to define a power domain and its characteristics. for example, if this command is used by UPF-aware tools to define a set of blocks in the design that are treated as one power domain that is supplied differently to other blocks on the same chip. The idea behind this type of command is that power-aware tools read in the description of which blocks in a design can be powered up and down independently.

Content in UPF:

• Power domains: some time design have more than one power domain like multi Vdd design and sometimes only a single power domain design. In this group of elements share a common set of power supply.
• Supply rails: distribution of power in supply nets, ports, supply sets, power state
• Additional Protection By special cells: level shifters, isolation cells, power switches, retention registers

Isolation cells:

Isolations cells always used between two domains active mode domains and shut down mode domain.

Consider there are two power domains one D1 is in shutdown mode and D2 is in active mode, if data is passed through D1 to D2 this will not a valid data received at D2. To prevent this condition we insert an isolation cell b/w these two power domains to clamp a known value at the D2 otherwise it will give unknown value.

Shut down domain outputs may be floating outputs and this could be a problem when other active domains get these floating outputs as an input. This could affect the proper functioning of the active domain.

These cells are also called “clamp” because these cells convert the invalid or floating outputs to a known value or clamp it to some specified known value.

Level shifter:

The chip may be divided into multiple voltage domains, where each domain is optimized for the needs of certain circuits. For example a system on a chip might use a high supply voltage for memories to ensure cell stability, a medium voltage for a processor and low voltage for IO peripherals. Some of the challenges in using voltage domain include voltage levels for signals that cross domains, selecting which circuits belongs in which domain

Whenever a signal is going from low domain to high domain there will not be full output swing available at the output of high domain or vice versa. In this condition we required level shifter to shift up or down the voltage level according to the requirement.

Let us consider one example, there are two designs with different power domains, one design is working on 1.5 v and the other is working on 1 v power supply. Now if the signal is passed from 1.5v domain to 1 v domain then wrong logic is interpreted by 1v domain. So to prevent this level sifter are inserted b/w two domains. The main function of the level shifter is to shift the voltage level according to the requirement of voltage levels.

Retention Registers:

To reduce power consumption when the devices are not in use, the power domain is switched off for those devices. When the design blocks are in switched off or sleep mode, data in all flip-flops contained within a block will be lost. If the designer desires to retain this state then retention registers are used. Retention register requires D flip-flop and latch and required always-on supply to retain the data. Using the retention register area required more as compared to normal flop because here we are using flip-flop with always-on supply. So the area required more when we are using retention registers.

Always On cells:

These cells are always on irrespective of where they are placed. Generally buffer and inverters are used for always ON cells. Always cells are also present in UPF. They can be a special cell or regular buffer. If they are special cells they have their own secondary power supply and placed anywhere in the design.

If they are regular buffer/inverters they require always-on cells and restrict the placement of these types of cells in the specific region

For example if data needs to be routed through or from the sleep block domain to active block domain and distance between both domains is very long or driving load is also very large then buffer might be needed to drive the long nets from one domain to another.