VLSI PHYSICAL DESIGN FLOW

 Physical design:

HERE ARE THE FULL DETAILS ABOUT THE PHYSICAL DESIGN FLOW:

(Click the below link to explain the concepts)

1. PHYSICAL DESIGN INPUTS & DESCRIPTION
2. PHYSICAL DESIGN SANITY CHECKS
   
3. WHAT IS FLOORPLAN?
   
4. PHYSICAL ONLY CELLS
   
5. POWER PLANNING
   
6. UPF & SPECIAL CELLS FOR POWER PLANNING
   
7. SOURCES OF POWER DISSIPATION
   
8. CLOCK TREE SYNTHESIS - PART1
   
9. CLOCK TREE SYNTHESIS - PART2
   
10. CLOCK TREE SYNTHESIS - PART3
    
11. CLOCK TREE ROUTING ALGORITHMS

Physical design means --->> netlist (.v ) converted into GDSII form(layout form)

logical connectivity of cells converted into physical connectivity.

During physical design, all design components are instantiated with their geometric representations. In other words, all macros, cells, gates, transistors, etc., with fixed shapes and sizes per fabrication layer, are assigned spatial locations (placement) and have appropriate routing connections (routing) completed in metal layers.

Physical design directly impacts circuit performance, area, reliability, power, and manufacturing yield. Examples of these impacts are discussed below.

1. Performance: long routes have significantly longer signal delays.
2. Area: placing connected modules far apart results in larger and slower chips.
3. Reliability: A large number of vias can significantly reduce the reliability of the circuit.
4. Power: transistors with smaller gate lengths achieve greater switching speeds at the cost of higher leakage current and manufacturing variability; larger transistors and longer wires result in greater dynamic power dissipation.
5. Yield: wires routed too close together may decrease yield due to electrical shorts occurring during manufacturing, but spreading gates too far apart may also undermine yield due to longer wires and a higher probability of opens

Due to its high complexity, physical design is split into several key steps (Fig. 1).

• Partitioning: breaks up a circuit into smaller sub-circuits or module which can each be designed or analyzed individually.
• Floorplanning: determines the shapes and arrangement of sub-circuits or modules, as well as the locations of external ports and IP or macro-blocks
• Power and ground routing (power planning): often intrinsic to floorplanning, distributes power (VDD) and ground (GND) nets throughout the chip.
• Placement: finds the spatial locations of all cells within each block.
• Clock network synthesis: determines the buffering, gating (e.g., for power management) and routing of the clock signal to meet prescribed skew and delay requirements
• Global routing: allocates routing resources that are used for connections; example resources include routing tracks in the channel and in the switch box
• Detailed routing: assigns routes to specific metal layers and routing tracks within the global routing resources.
• Timing closure: optimizes circuit performance by specialized placement or routing techniques 

**GDS- Graphical Data system

1. The physical design is the process of transforming a circuit description into the physical layout, which describes the position of cells and routes for the interconnections between them.
2. The main concern is the physical design of VLSI-chips is to find a layout with minimal area, further the total wire length has to be minimized. For some critical nets there are hard limitations for the maximal wire length.

The main steps in the ASIC PHYSICAL DESIGN flow are: 

1. Design netlist (after synthesis)                    
2. Floorplanning 
3. Power planning
4. placement
5. Clock Tree Synthesis(CTS)
6. Routing
7. Physical verification
8. GDSII generation                                              

Physical verification:

After physical design is completed, the layout must be fully verified to ensure correct electrical and logical functionality. Some problems found during physical verification can be tolerated if their impact on chip yield is negligible. Therefore, at this stage, layout changes are usually performed manually by experienced design engineers.

• Design rule checking (DRC): verifies that the layout meets all technology-imposed constraints. DRC also verifies layer density for chemical-mechanical polishing (CMP).
• Layout vs. schematic (LVS): checking verifies the functionality of the design. From the layout, a netlist is derived and compared with the original netlist produced from logic synthesis or circuit design.
• Parasitic extraction: derives electrical parameters of the layout elements from their geometric representations; with the netlist, these are used to verify the electrical characteristics of the circuit.
• Antenna rule checking: seeks to prevent antenna effects, which may damage transistor gates during manufacturing plasma-etch steps through the accumulation of excess charge on metal wires that are not connected to PN junction node
• Electrical rule checking (ERC): verifies the correctness of power and ground connections, and that signal transition times (slew), capacitive loads and fan-outs are appropriately bounded
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EDA Tools:

1.P&R

Synopsys: ICCI, ICCII, DC COMPILER

cadence: Encounter, innovus

2. TIMING ANALYSIS

Synopsys: Primetime

cadence: tempus

3. physical verification:

Synopsys:Hercules

cadence: Assura

mentor: calibre(mostly used)

4.RC Extraction:

Synopsys: StarRCXT

5.formal verification:

Synopsys: formality